1. Field of the Invention
The present invention is directed in general to signal timing measurements. In one aspect, the present invention relates to an on-chip method and system for calibrating, measuring, and testing integrated circuit device signals.
2. Description of the Related Art
The performance and functionality of various electronic circuits, whether integrated as discrete components or in System-on-a-Chip (SoC) applications, may be evaluated by measuring internal and external signals developed by the electronic circuits. For example, memory subsystems (such as double data rate (DDR) synchronous dynamic random access memory (SDRAM)) require precise timing and testing of the data and clock pins signals to ensure proper operation and compliance with electrical and/or timing specifications, especially as processor and DRAM speeds increase. Conventional signal measurement techniques use external automated test equipment (“ATE”) tools which are expensive, slow, and complicated to operate. On-die measurement circuits can also be used, such as delay-chain circuits with a single capture flip-flop, delay locked loop (DLL) circuits for delaying a phase locked loop clock with an interpolator circuit, and circuits with delay-chain and multiple capture flip-flops having an identical clock signal to measure signal skew and jitter. In addition, clocks with different calibration frequencies can be applied to measure a signal across multiple clock cycles using complex control and support logic. Unfortunately, existing signal measurement techniques entail undue circuit complexity and cost, as well as limited measurement granularity or resolution.